The art of designing and implementing Large Scale Integration (LSI) devices and very large scale integration (VLSI) devices in digital logic has become more complex and sophisticated in recent years. Sophisticated software design tools and automated techniques have replaced prior pencil and paper engineering practices once used to design semiconductor devices. As semiconductor devices have become more complex in terms of circuitry and design, with shrinking device geometry, requirements for data transmission between such devices and on individual ones of such devices has also become more complex and demanding to maintain in operation.
The preferred system for transmitting data between IC devices has long been the system of parallel data transfer. The current method of parallel data transfer incorporates the use of a plurality of separate data-signal transmission paths in parallel. Data passed between two communicating devices travels across a circuit board on a bus, which comprises a plurality of parallel traces or lines. For a 16-bit system, for example, a parallel system would include a separate trace for each bit (16 traces) plus control lines.
Generally speaking, much operational and specification data regarding the manufacture and operation of VLSI and LSI type devices is known and available in the art. Manufacturers of such devices provide exhaustive documentation, and virtually all of such documentation is available to the skilled artisan. Therefore, detailed architectural and functional descriptions of known IC devices are not provided herein. It is enough to say that parallel data must be clocked, synchronized and latched in order to enable successful transmission of the data from a propagating device to a receiving device over a circuit board containing a substantially large number of traces.
Another system for transferring data in general, and also sometimes used for transferring data between IC devices, is the system of serial data transfer. The current method of transferring high-bandwidth serial data between IC devices involves the use of encoding and decoding circuits on each communicating device to manipulate or convert the incoming parallel data, so that it may be transmitted serially across a circuit board from one device to another. For example, a parallel-to-serial data converter in a sending device enables parallel data to be prepared for serial, one-way transmission over a single data line. A decoder circuit in a receiving device decodes the transmitted serial data (using, e.g., a pre-determined decoding scheme), then processes the data. At a given clock speed, serial data transfer is typically slower than parallel data transfer. Therefore, a higher-speed clock is typically used with the serial method to increase the speed with which the serial data is transmitted between devices.
Another problem with current technology is that analog circuitry is typically required in the sending and receiving IC devices to accommodate serial data transfer between the IC devices. Analog circuitry is notoriously more difficult to implement than digital circuitry, and makers of digital IC devices are not anxious to suffer the yield losses attendant on adding analog circuitry to their devices.
Still, even with the known and perceived disadvantages of serial data transmission, the high cost and complexity of parallel data transmission systems is an increasing problem. As computing systems have matured from 4 to 8 to 16 to 32 bit words, and as microprocessors and memories (for example) have become more functional and sophisticated, the number of traces and pins necessary to accomplish adequate transmission has increased dramatically. It is, for example, now common to have plural sets of parallel data transmission pathways serving a single IC device. The high number of traces necessary on a PC board (for example) makes such support systems enormously complex and expensive to design and manufacture. Moreover, every trace demands a separate pin on the IC device. Many devices have more than two hundred pins, and future devices may demand even more. The higher and higher pin count makes such devices more complex to build and increases losses (lower yield) in fabrication.
A serial communication system that may be used between two or more IC devices is described in U.S. Pat. No. 6,233,394 filed Aug. 17, 1999, and referenced above in the Cross-Reference section. The system described in the above-mentioned patent utilizes a separate master chip connected to the sending and receiving IC devices of the serial communication system. In addition, the master chip is described as having a clock generator, and circuitry for affecting serial data transmission and control between the master chip and the IC devices. A slave component is also included on each IC device for transforming data between parallel and serial data formats, and for sending and receiving a serial data stream. The intervening master chip provides a clock signal to each of the slave components for gating serial data communication, and manages all communication between the two slave components. In a preferred embodiment, all circuitry in the slave components is digital circuitry, and all analog circuitry is implemented on the master chip. Also in a preferred embodiment, each slave component periodically checks the phase between the received data and clock streams, and inserts a correction code into the data stream sent back to the master chip, so that the master chip can regularly correct the phase for the clock and data streams sent to each slave.
One challenge in implementing parallel-in-to-serial-out (PISO) converters is that, in order to maintain the desired clock speed of the serial portion of the transmission, the entire converter is typically clocked at the same high speed. This means that considerable power is consumed and cross contamination Oitter) between the traces is more likely to occur at higher levels. The problem increases in chips that process larger bit-size words.
It is desired that extremely high serial clock rates be achieved without requiring maximum power consumption on the processing (PISO) chip. Therefore, what is clearly needed is a method for reducing overall power requirements of a PISO converter, while maintaining a high clock-rate for gating out serial data from a parallel data source.